As it is well known, recently portable electronic devices have been the driving force behind development in the electronic field. In particular, in recent times research has embarked on the reduction of the supply voltage of electronic devices used in applications to increase the duration of battery operation. Naturally, since not all the components scaled in supply starting from a same voltage are available on an electronic device board, today many devices are realized using different supply voltages.
In particular, for memory electronic devices the supply voltage of the outputs (output buffers) and of the inputs (input buffers), generally indicated as VDDQ, is maintained separated from the supply voltage of the memory core, indicated with VDD.
This choice allows maintaining the loads of the outputs unaltered, thus avoiding a request for different technology approaches both by the client using memory devices, who, otherwise, should realize boards with more controlled capacitances, resistances and inductances, and by the component builder who, otherwise, should consider the test machines currently used.
The last years have shown the passage from memory devices supplied with 24V to those supplied with 12V and, more recently, to supplies with 5V, to now current devices supplied with 3V.
Let's now analyze a “Flash” memory electronic device, shown, for example, in the schematic block diagram of FIG. 1. Naturally, similar considerations can be made on all the devices wherein the supply voltage is to be scaled.
The “Flash” memory device, globally indicated with 1, has a first supply voltage VDD used to supply a core block 2 which, in general, comprises decoders, reading circuits, boosters and a memory comprising a plurality of memory cells organized in matrix. In addition, the device 1 has a second supply voltage VDDQ, which suitably supplies an output buffer 3 and an input buffer 4.
Advantageously, the separation introduced between the two supply voltages VDD and VDDQ serves to avoid possible noise produced by the switching of the outputs of the output buffer 3 and of the input buffer 4 that affects the functionality of the components of the core block 2 and in particular of the core components.
Several problems arise when making the “Flash” memory devices work with a first supply voltage applied at the input VDD of about 0.9V as required, as per current requests. In particular, in the decoder circuits comprised within the core block 2 of the device 1. They need high voltage transistors, since “Flash” memory cells operate with voltage values being much higher than the value of 0.9V, on the order of about 10V. In order for the decoders to work quickly, at least for the reading operations, transistors would be required having a very low threshold but with a thick oxide for the writing and erasing operations. Naturally, the two requests are in conflict with each other.
Considering further components of the block 2, such as the reading circuits, they allow applying predetermined voltage values to a decoded memory cell making it operative. This operation requires a current-voltage conversion which, however, typically needs voltage stability and, simultaneously, a predetermined voltage value sufficient for making the conversion. Naturally, the requested low voltage supply values, such as 0.9V, need a greater accuracy and precision in the components used.
Current memory devices comprise, inside the block 2, inner boosters obtained by way of charge pumps with stages formed by diodes and capacitors that allow generating the different voltages required by the components of the block 2. The low supply voltages, such as 0.9V, then require an increase of the number of the stages with a consequent area increase and loss of efficiency or a decrease of the output resistance of the charge pump.
The core or the matrix of the “Flash” memory device being supplied with voltages equal to 0.9V requires the use of low threshold voltage transistors to avoid the slowdown of the operations to be performed.
Let's now take some possible memory device configurations further by considering the functionality of the supply voltages VDD and VDDQ. We refer to five different configurations summarized in the table of FIG. 2 and represented by way of schematic block diagrams in FIGS. 3 to 7.
In the first case, shown in FIG. 3, the core block 2, of the “Flash” memory device 1 is supplied by a voltage equal to about 3V while the supply voltage of the output buffer 3 and input buffer 4 is equal to about 1.5V. In this case, requiring a first supply voltage equal to about 0.9V a Step-up or booster 6 is interposed between the first supply voltage VDD and core block 2 allowing bringing the voltage at the input of the core to the necessary value of about 3V. While a second supply voltage VDDQ of about 18V directly supplies the output buffer 3 and input buffer 4.
In the second example shown in FIG. 4 a “Flash” memory device 1 has a core block 2 supplied by a voltage of about 1.8V similar to the supply voltage of the output and input buffers 3,4. In this case, requiring a first supply voltage equal to about 0.9V a Step-up block 6 is interposed between the first voltage VDD and the core block 2 which allows bringing the input voltage at the core block 2 to the necessary value of about 1.8V, while the second supply voltage VDDQ of about 1.8V directly supplies the input buffer 4 and output buffer 3.
Similar is the case shown in FIG. 5, wherein a “Flash” memory device 1 shows a Step up block 6 interposed between a first supply voltage VDD set at about 0.9V and the input of a core block 2 supplied by a voltage equal to about 18V, while a second supply voltage VDDQ of about 3V directly supplies the input buffer 4 and output buffer 3.
Also in the case of FIG. 6, a “Flash” memory device 1 has a Step-up block 6 interposed between a first supply voltage VDD of about 0.9V and an input of a core block 2 supplied with 3V, while a second supply voltage VDDQ directly supplies the input buffer 4 and output buffer 3 supplied with about 3V.
A different situation is reported for the example in FIG. 7 wherein a “Flash” memory device 1 has a core block 2 and an input buffer 4 supplied by a voltage of about 1.8V or 3V, while an output buffer 3 is supplied with about 0.9V. In this case, there will be a single supply voltage VDD which directly supplies the output buffer 3 and by way of the interposition of a Step up block 6 between the core block 2 and the input buffer 4.
The problem is that of providing a memory device having such structural and functional characteristics as to allow it to be supplied with low supply voltages, on the order of 0.9V, by using commercially available components and maintaining the compatibility of the output pins of a current memory device, overcoming the limits and/or drawbacks still affecting the devices realized according to the prior art.